I made a RISC-V SoC!

I recently finished building a RISC-V RV32I core on my GOWIN GW1NR-9 based FPGA (here’s the exact board). This was my second attempt ever at implementing some sort of instruction set. First was a CHIP-8 emulator I wrote in Python.

I want to document the features of the SoC here as I keep working on it and adding new stuff.

Current Hardware:

• CPU Core implementing the 32-bit Base Integer instruction set (RV32I)
• Memory-mapped UART TX, RX
• 6 onboard memory-mapped LEDs

Current Software:

• super minimal C library with getc, getchar, putchar implemented in RISC-V assembler using the ilp32 ABI
• headers with #defines for the memory map
• working on a no-std Rust example
• looking at picolibc as a candidate for a standard library
• working on an SPI peripheral for external Flash+RAM
• looking at adding a Wishbone or AXI bus for easier integration of pre-built open-source peripherals into the SoC

Fun tools I learned about while building this:

• yosys
• nextpnr
• Project Apicula

Some related links:

• Verilog: HDLBits
• riscv-gnu-toolchain
• Open-Source RISC-V: Hazard3, SERV, Bruno Levy’s LearnFPGA Repository
• RISC-V Specification